Çѱ¹Á¤º¸Åë½ÅÇÐȸ ³í¹®Áö (Journal of the Korea Institute of Information and Communication Engineering)
Current Result Document :
ÇѱÛÁ¦¸ñ(Korean Title) |
´ÙÁß ºí·Ï ¾ÏÈ£ ¾Ë°í¸®µëÀ» Áö¿øÇÏ´Â ¾ÏÈ£ ÇÁ·Î¼¼¼ |
¿µ¹®Á¦¸ñ(English Title) |
A Crypto-processor Supporting Multiple Block Cipher Algorithms |
ÀúÀÚ(Author) |
Á¶¿í·¡
±è±â»Ý
¹è±âö
½Å°æ¿í
Wook-Lae Cho
Ki-Bbeum Kim
Gi-Chur Bae
Kyung-Wook Shin
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¿ø¹®¼ö·Ïó(Citation) |
VOL 20 NO. 11 PP. 2093 ~ 2099 (2016. 11) |
Çѱ۳»¿ë (Korean Abstract) |
PRESENT, ARIA, AESÀÇ 3°¡Áö ºí·Ï ¾ÏÈ£ ¾Ë°í¸®µëÀ» Áö¿øÇÏ´Â ´ÙÁß ¾ÏÈ£ ÇÁ·Î¼¼¼ ¼³°è¿¡ ´ëÇØ ±â¼úÇÑ´Ù. ¼³°èµÈ ¾ÏÈ£ ĨÀº PRmo (PRESENT with mode of operation), AR_AS (ARIA_AES) ±×¸®°í AES-16b ÄÚ¾î·Î ±¸¼ºµÈ´Ù. 64-ºñÆ® ºí·Ï¾ÏÈ£ PRESENT¸¦ ±¸ÇöÇÏ´Â PRmo ÄÚ¾î´Â 80-ºñÆ®, 128-ºñÆ® Å° ±æÀÌ¿Í ECB, CBC, OFB, CTRÀÇ 4°¡Áö ¿î¿µ¸ðµå¸¦ Áö¿øÇÑ´Ù. 128-ºñÆ®, 256-ºñÆ® Å° ±æÀ̸¦ Áö¿øÇÏ´Â AR_AS ÄÚ¾î´Â 128-ºñÆ® ºí·Ï¾ÏÈ£ ARIA¿Í AES¸¦ ÀÚ¿ø°øÀ¯ ±â¹ýÀ» Àû¿ëÇÏ¿© ´ÜÀÏ µ¥ÀÌÅÍ Æнº·Î ÅëÇÕ ±¸ÇöµÇ¾ú´Ù. 128-ºñÆ® Å° ±æÀ̸¦ Áö¿øÇÏ´Â AES-16b ÄÚ¾î´Â Àú¸éÀû ±¸ÇöÀ» À§ÇØ 16-ºñÆ®ÀÇ µ¥ÀÌÅÍÆнº·Î ¼³°èµÇ¾ú´Ù. °¢ ¾ÏÈ£ ÄÚ¾î´Â on-the-fly Å° ½ºÄÉÁÙ·¯¸¦ Æ÷ÇÔÇÏ°í ÀÖÀ¸¸ç, Æò¹®/¾ÏÈ£¹® ºí·ÏÀÇ ¿¬¼ÓÀûÀÎ ¾ÏÈ£/º¹È£È 󸮰¡ °¡´ÉÇÏ´Ù. FPGA °ËÁõÀ» ÅëÇØ ¼³°èµÈ ´ÙÁß ºí·Ï ¾ÏÈ£ ÇÁ·Î¼¼¼ÀÇ Á¤»ó µ¿ÀÛÀ» È®ÀÎÇÏ¿´´Ù. 0.18§ °øÁ¤ÀÇ CMOS ¼¿ ¶óÀ̺귯¸®·Î ÇÕ¼ºÇÑ °á°ú, 54,500 GEs (gate equivalents)·Î ±¸ÇöÀÌ µÇ¾úÀ¸¸ç, 55 MHzÀÇ Å¬·Ï ÁÖÆļö·Î µ¿ÀÛ °¡´ÉÇÏ´Ù.
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¿µ¹®³»¿ë (English Abstract) |
This paper describes a design of crypto-processor that supports multiple block cipher algorithms of PRESENT, ARIA, and AES. The crypto-processor integrates three cores that are PRmo (PRESENT with mode of operation), AR_AS (ARIA_AES), and AES-16b. The PRmo core implementing 64-bit block cipher PRESENT supports key length 80-bit and 128-bit, and four modes of operation including ECB, CBC, OFB, and CTR. The AR_AS core supporting key length 128-bit and 256-bit integrates two 128-bit block ciphers ARIA and AES into a single data-path by utilizing resource sharing technique. The AES-16b core supporting key length 128-bit implements AES with a reduced data-path of 16-bit for minimizing hardware. Each crypto-core contains its own on-the-fly key scheduler, and consecutive blocks of plaintext/ciphertext can be processed without reloading key. The crypto-processor was verified by FPGA implementation. The crypto-processor implemented with a 0.18§ CMOS cell library occupies 54,500 gate equivalents (GEs), and it can operate with 55 MHz clock frequency.
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Å°¿öµå(Keyword) |
ºí·Ï¾ÏÈ£
ARIA ¾Ë°í¸®µë
AES ¾Ë°í¸®µë
PRESENT ¾Ë°í¸®µë
Á¤º¸º¸¾È
Block Cipher
ARIA algorithm
AES algorithm
PRESENT algorithm
information security
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ÆÄÀÏ÷ºÎ |
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